One of the fastest growing segments of the semiconductor industry is the manufacture of multi-chip modules (MCM). Multi-chip modules are being increasingly used in computers to form PC chip sets and in telecommunication items such as modems and cellular telephones. In addition, consumer electronic products such as watches and calculators typically include multi-chip modules.
With a multi-chip module, non-packaged or bare dice (i.e., chips) are secured to a secured to a substrate (e.g., printed circuit board) using an adhesive. Electrical connections are then made directly to the bond pads on each die and to electrical leads on the substrate. Non-packaged dice are favored because the costs associated with manufacturing and packaging the dice are substantially reduced. This is because the processes for packaging semiconductor dice are extremely complex and costly.
This is illustrated with reference to FIG. 1. A fabrication process for a packaged die begins with a semiconductor wafer on which a large number of semiconductor dice have been formed by doping, masking, deposition of metals, and etching a silicon substrate. Initially the wafer is probed and mapped, step 10. Wafer mapping is performed to test the gross functionality of the dice on the wafer. The nonfunctional dice are mechanically marked or mapped in software. Next, the mapped wafer is mounted on a carrying film, step 12. The carrying film allows the wafer to be mechanically transported and provides support for the saw cutting procedure.
Next, the dice are singulated using a diamond saw, step 14. Each singulated die must then be attached to a metal lead frame, step 16. A single lead frame supports several semiconductor dice for packaging and provides the leads for the packaged die. Die attach to the lead frame is typically accomplished using a liquid epoxy adhesive that must be cured with heat, step 18. Next, a wire bond process, step 20, is performed to attach thin bond wires to the bond pads on the die and to the lead fingers of the lead frame. A protective coating such as a polyimide film is then applied to the wire bonded die, step 22, and this coating is cured, step 24.
The semiconductor die is then encapsulated using an epoxy molding process, step 26. Alternately premade ceramic packages with a ceramic lid may be used to package the die. Next, the encapsulated die is laser marked for identification, step 28. This is followed by an electrolytic deflash for removing excess encapsulating material, step 30, an encapsulation cure, step 32 and cleaning with a citric bath, step 34. Next, the lead frame is trimmed and formed, step 36, to form the leads of the package, and the leads are plated using a wave solder process (tin or plating), step 38. This is followed by scanning, step 40, in which the packaged dice are optically scanned for defects and then an inventory, step 42.
The packaged die is then subjected to a hot pregrade test, step 44 in which it is tested and then marked, step 46. A series of burn-in tests, steps 48 and 50, and a hot final test, step 52 are then performed to complete the testing procedure. This is followed by another scan, step 54, a visual inspection, step 56, a quality control check, step 58, and packaging for shipping, step 60. The finished goods are represented at step 62.
As is apparent, the packaging process (steps 16-40) for manufacturing packaged dice requires a large amount of time, materials and capital investment to accomplish. Thus one advantage of manufacturing bare or unpackaged dice is that the above manufacturing process can be greatly simplified because all of the packaging steps are eliminated. A disadvantage of manufacturing unpackaged dice is that transport and testing of the dice is more difficult to accomplish.
With unpackaged dice, semiconductor manufacturers are required to supply dice that have been tested and certified as known good die (KGD). Known-good-die (KGD) is a collective term that connotes unpackaged die having the same quality and reliability as the equivalent packaged product. This has led to a need in the art for manufacturing processes suitable for fabricating and testing bare or unpackaged semiconductor die.
For test and burn-in of bare die, a carrier must replace a conventional single chip package in the manufacturing process. The carrier includes an interconnect that allows a temporary electrical connection to be made between external test circuitry and the bond pads of the die. In addition, such a carrier must be compatible with semiconductor manufacturing equipment and allow the necessary test procedures to be performed without damaging the die. The bond pads on a die are particularly susceptible to damage during the test procedure.
In response to the need for unpackaged die, different semiconductor manufacturers have developed carriers for testing known good die. As an example, carriers for testing unpackaged die are disclosed in U.S. Pat. No. 4,899,107 to Corbett et al. and U.S. Pat. No. 5,302,891 to Wood et al., which are assigned to Micron Technology, Inc. Other carriers for unpackaged die are disclosed in U.S. Pat. No. 5,123,850 to Elder et al., and U.S. Pat. No. 5,073,117 to Malhi et al., which are assigned to Texas Instruments.
One of the key design considerations for a carrier is the method for establishing electrical communication between the die and interconnect. With some carriers, the die is placed face down in the carrier and biased into contact with the interconnect. The interconnect includes contacts that physically align with and contact the bond pads or test pads of the die. Exemplary contact structures include wires, needles, and bumps. The mechanisms for making electrical contact include piercing the native oxide of the bond pad with a sharp point, breaking or burnishing the native oxide with a bump, or moving across the native oxide with a contact adapted to scrub away the oxide. In general, each of these contact structures is adapted to form a low-resistance “ohmic contact” with the bond pad. Low-resistance is a negligible resistance. An ohmic contact is one in which the voltage appearing across the contact is proportional to the current flowing for both directions of current flow. Other design considerations for a carrier include electrical performance over a wide temperature range, thermal management, power and signal distribution, and the cost and reusability of the carrier.
The present invention is directed to a method for manufacturing known good die. In addition, the present invention is directed to an apparatus for manufacturing known good die including carriers for testing bare die and apparatus for automatically loading and unloading bare die into the carriers.